The common clk framework is an interface to control the system clock nodes. This may come in the form of clock gating, rate adjustment, muxing or other operations.
This framework is enabled with the CONFIG_COMMON_CLKoption.
Related Xilinx Wiki: Common Clock Framework
More details can be found here.
The system clock summary can be read from here:
In [1]:
cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty
clock count count count rate accuracy phase cycle
---------------------------------------------------------------------------------------------
cpll 0 0 0 0 0 0 50000
misc_clk_0 8 8 0 99999000 0 0 50000
ref_clk 2 2 2 33333333 0 0 50000
rpu_postclk 0 0 0 33333333 0 0 50000
rpu_presrc 1 1 1 33333333 0 0 50000
rpu_pll 1 1 1 2999999970 0 0 50000
rpu_pll_out 1 1 1 749999993 0 0 50000
rpll 2 2 1 749999993 0 0 50000
gem_tsu_ref_mux 1 1 1 749999993 0 0 50000
gem_tsu_ref_div1 1 1 1 249999998 0 0 50000
gem_tsu_ref 1 1 1 249999998 0 0 50000
gem_tsu 1 1 0 249999998 0 0 50000
gem_tsu_lb 0 0 0 249999998 0 0 50000
gem1_ref_mux 0 0 0 749999993 0 0 50000
gem1_ref_div1 0 0 0 124999999 0 0 50000
gem1_ref 0 0 0 124999999 0 0 50000
gem1_tx_mux 0 0 0 124999999 0 0 50000
gem1_tx 0 0 0 124999999 0 0 50000
gem0_ref_mux 1 1 0 749999993 0 0 50000
gem0_ref_div1 1 1 0 25000000 0 0 50000
gem0_ref 2 2 0 25000000 0 0 50000
gem0_tx_mux 1 1 0 25000000 0 0 50000
gem0_tx 1 1 0 25000000 0 0 50000
iou_switch_mux 0 0 0 749999993 0 0 50000
iou_switch_div1 0 0 0 249999998 0 0 50000
iou_switch 0 0 0 249999998 0 0 50000
cpu_r5_mux 0 0 0 749999993 0 0 50000
cpu_r5_div1 0 0 0 374999997 0 0 50000
cpu_r5 0 0 0 374999997 0 0 50000
cpu_r5_ocm2 0 0 0 374999997 0 0 50000
cpu_r5_ocm 0 0 0 374999997 0 0 50000
cpu_r5_core 0 0 0 374999997 0 0 50000
lpd_top_switch_mux 0 0 0 749999993 0 0 50000
lpd_top_switch 0 0 0 374999997 0 0 50000
adma 0 0 0 374999997 0 0 50000
rpll_to_xpd 0 0 0 249999998 0 0 50000
apu_postclk 0 0 0 33333333 0 0 50000
apu_presrc 0 0 0 33333333 0 0 50000
apu_pll 0 0 0 3999999960 0 0 50000
apu_pll_out 0 0 0 999999990 0 0 50000
apll 0 0 0 999999990 0 0 50000
acpu_mux 0 0 0 999999990 0 0 50000
acpu_div1 0 0 0 999999990 0 0 50000
acpu 0 0 0 999999990 0 0 50000
fpd_top_switch_mux 0 0 0 999999990 0 0 50000
fpd_top_switch 0 0 0 499999995 0 0 50000
apll_to_xpd 0 0 0 499999995 0 0 50000
noc_postclk 0 0 0 33333333 0 0 50000
noc_presrc 0 0 0 33333333 0 0 50000
noc_pll 0 0 0 3799999962 0 0 50000
noc_pll_out 0 0 0 949999991 0 0 50000
npll 0 0 0 949999991 0 0 50000
npll_to_xpd 0 0 0 949999991 0 0 50000
pmc_postclk 0 0 0 33333333 0 0 50000
pmc_presrc 1 1 1 33333333 0 0 50000
pmc_pll 1 1 1 2399999976 0 0 50000
pmc_pll_out 1 1 1 1199999988 0 0 50000
ppll 2 3 3 1199999988 0 0 50000
sd_dll_ref_mux 0 0 0 1199999988 0 0 50000
sd_dll_ref_div1 0 0 0 1199999988 0 0 50000
sd_dll_ref 0 0 0 1199999988 0 0 50000
hsm1_ref_mux 0 0 0 1199999988 0 0 50000
hsm1_ref_div1 0 0 0 133333332 0 0 50000
hsm1_ref 0 0 0 133333332 0 0 50000
hsm0_ref_mux 0 0 0 1199999988 0 0 50000
hsm0_ref_div1 0 0 0 33333333 0 0 50000
hsm0_ref 0 0 0 33333333 0 0 50000
npi_ref_mux 0 0 0 1199999988 0 0 50000
npi_ref_div1 0 0 0 299999997 0 0 50000
npi_ref 0 0 0 299999997 0 0 50000
spare_ref_mux 0 0 0 1199999988 0 0 50000
spare_ref_div1 0 0 0 599999994 0 0 50000
spare_ref 0 0 0 599999994 0 0 50000
cfu_ref_mux 0 0 0 1199999988 0 0 50000
cfu_ref_div1 0 0 0 299999997 0 0 50000
cfu_ref 0 0 0 299999997 0 0 50000
pmc_pl3_ref_mux 0 0 0 1199999988 0 0 50000
pmc_pl3_ref_div1 0 0 0 239999998 0 0 50000
pmc_pl3_ref 0 0 0 239999998 0 0 50000
pmc_pl2_ref_mux 0 0 0 1199999988 0 0 50000
pmc_pl2_ref_div1 0 0 0 239999998 0 0 50000
pmc_pl2_ref 0 0 0 239999998 0 0 50000
pmc_pl1_ref_mux 0 0 0 1199999988 0 0 50000
pmc_pl1_ref_div1 0 0 0 239999998 0 0 50000
pmc_pl1_ref 0 0 0 239999998 0 0 50000
pmc_pl0_ref_mux 0 0 0 1199999988 0 0 50000
pmc_pl0_ref_div1 0 0 0 99999999 0 0 50000
pmc_pl0_ref 0 0 0 99999999 0 0 50000
dft_osc_ref_mux 0 0 0 1199999988 0 0 50000
dft_osc_ref_div1 0 0 0 399999996 0 0 50000
dft_osc_ref 0 0 0 399999996 0 0 50000
test_pattern_ref_mux 0 0 0 1199999988 0 0 50000
test_pattern_ref_div1 0 0 0 199999998 0 0 50000
test_pattern_ref 0 0 0 199999998 0 0 50000
i2c_ref_mux 0 0 0 1199999988 0 0 50000
i2c_ref_div1 0 0 0 99999999 0 0 50000
i2c_ref 0 0 0 99999999 0 0 50000
pmc_lsbus_ref_mux 0 0 0 1199999988 0 0 50000
pmc_lsbus_ref 0 0 0 99999999 0 0 50000
sdio1_ref_mux 1 1 1 1199999988 0 0 50000
sdio1_ref_div1 1 1 1 199999998 0 0 50000
sdio1_ref 1 1 1 199999998 0 0 50000
sdio0_ref_mux 0 0 0 1199999988 0 0 50000
sdio0_ref_div1 0 0 0 199999998 0 0 50000
sdio0_ref 0 0 0 199999998 0 0 50000
ospi_ref_mux 0 0 0 1199999988 0 0 50000
ospi_ref_div1 0 0 0 299999997 0 0 50000
ospi_ref 0 0 0 299999997 0 0 50000
qspi_ref_mux 0 1 1 1199999988 0 0 50000
qspi_ref_div1 0 1 1 199999998 0 0 50000
qspi_ref 0 1 1 199999998 0 0 50000
ppll_to_xpd 3 5 4 599999994 0 0 50000
usb3_dual_ref_mux 1 1 1 599999994 0 0 50000
usb3_dual_ref_div1 1 1 1 20000000 0 0 50000
usb3_dual_ref 1 1 1 20000000 0 0 50000
dbg_tstmp_mux 0 0 0 599999994 0 0 50000
dbg_tstmp_div1 0 0 0 299999997 0 0 50000
dbg_tstmp 0 0 0 299999997 0 0 50000
timestamp_ref_mux 0 0 0 599999994 0 0 50000
timestamp_ref_div1 0 0 0 99999999 0 0 50000
timestamp_ref 0 0 0 99999999 0 0 50000
dbg_lpd_mux 0 0 0 599999994 0 0 50000
dbg_lpd_div1 0 0 0 299999997 0 0 50000
dbg_lpd 0 0 0 299999997 0 0 50000
i2c1_ref_mux 0 1 1 599999994 0 0 50000
i2c1_ref_div1 0 1 1 99999999 0 0 50000
i2c1_ref 0 1 1 99999999 0 0 50000
i2c0_ref_mux 0 1 1 599999994 0 0 50000
i2c0_ref_div1 0 1 1 99999999 0 0 50000
i2c0_ref 0 1 1 99999999 0 0 50000
can1_ref_mux 0 0 0 599999994 0 0 50000
can1_ref_div1 0 0 0 149999999 0 0 50000
can1_ref 0 0 0 149999999 0 0 50000
can1_clk 0 0 0 74999999 0 0 50000
can0_ref_mux 0 0 0 599999994 0 0 50000
can0_ref_div1 0 0 0 50000000 0 0 50000
can0_ref 0 0 0 50000000 0 0 50000
can0_clk 0 0 0 25000000 0 0 50000
spi1_ref_mux 0 0 0 599999994 0 0 50000
spi1_ref_div1 0 0 0 99999999 0 0 50000
spi1_ref 0 0 0 99999999 0 0 50000
spi0_ref_mux 0 0 0 599999994 0 0 50000
spi0_ref_div1 0 0 0 99999999 0 0 50000
spi0_ref 0 0 0 99999999 0 0 50000
uart1_ref_mux 0 0 0 599999994 0 0 50000
uart1_ref_div1 0 0 0 50000000 0 0 50000
uart1_ref 0 0 0 50000000 0 0 50000
uart0_ref_mux 0 0 0 599999994 0 0 50000
uart0_ref_div1 0 0 0 99999999 0 0 50000
uart0_ref 0 0 0 99999999 0 0 50000
usb0_bus_ref_mux 1 1 1 599999994 0 0 50000
usb0_bus_ref_div1 1 1 1 20000000 0 0 50000
usb0_bus_ref 1 1 1 20000000 0 0 50000
lpd_lsbus_mux 1 1 0 599999994 0 0 50000
lpd_lsbus 2 4 0 99999999 0 0 50000
ttc0 0 0 0 99999999 0 0 50000
ttc1 0 0 0 99999999 0 0 50000
ttc2 0 0 0 99999999 0 0 50000
ttc3 0 0 0 99999999 0 0 50000
dbg_fpd_mux 0 0 0 599999994 0 0 50000
dbg_fpd_div1 0 0 0 299999997 0 0 50000
dbg_fpd 0 0 0 299999997 0 0 50000
dbg_trace_mux 0 0 0 599999994 0 0 50000
dbg_trace_div1 0 0 0 119999999 0 0 50000
dbg_trace 0 0 0 119999999 0 0 50000
fpd_lsbus_mux 0 0 0 599999994 0 0 50000
fpd_lsbus 0 0 0 99999999 0 0 50000
psm_ref_mux 0 0 0 599999994 0 0 50000
psm_ref 0 0 0 299999997 0 0 50000
pl_alt_ref_clk 0 0 0 33333333 0 0 50000
alt_ref_clk 0 0 0 33333333 0 0 50000
gem1_rx_mux 0 0 0 0 0 0 50000
gem1_rx 0 0 0 0 0 0 50000
gem0_rx_mux 1 1 0 0 0 0 50000
gem0_rx 1 1 0 0 0 0 50000
muxed_iro_div4 0 0 0 0 0 0 50000
efuse_ref 0 0 0 0 0 0 50000
usb_suspend 0 0 0 0 0 0 50000
switch_timeout 0 0 0 0 0 0 50000
muxed_iro_div2 0 0 0 0 0 0 50000
sysmon_ref 0 0 0 0 0 0 50000
wdt 0 0 0 0 0 0 50000
iro_suspend_ref 0 0 0 0 0 0 50000
Orphan clocks summary:
In [2]:
cat /sys/kernel/debug/clk/clk_orphan_summary
enable prepare protect duty
clock count count count rate accuracy phase cycle
---------------------------------------------------------------------------------------------
gem1_rx_mux 0 0 0 0 0 0 50000
gem1_rx 0 0 0 0 0 0 50000
gem0_rx_mux 1 1 0 0 0 0 50000
gem0_rx 1 1 0 0 0 0 50000
muxed_iro_div4 0 0 0 0 0 0 50000
efuse_ref 0 0 0 0 0 0 50000
usb_suspend 0 0 0 0 0 0 50000
switch_timeout 0 0 0 0 0 0 50000
muxed_iro_div2 0 0 0 0 0 0 50000
sysmon_ref 0 0 0 0 0 0 50000
wdt 0 0 0 0 0 0 50000
iro_suspend_ref 0 0 0 0 0 0 50000
This will parse the system clock tree and create a diagraph named clktree.png in the same directory, and will display the same.
Make sure graphviz is configured:
In [ ]:
!dot -c
Let's run the demo:
In [ ]:
from pmutil import clktree
clktree.run_demo()
Content source: Xilinx/meta-petalinux
Similar notebooks: