In [1]:

    

#This notebook also uses the `(some) LaTeX environments for Jupyter`
#https://github.com/ProfFan/latex_envs wich is part of the
#jupyter_contrib_nbextensions package

from myhdl import *
from myhdlpeek import Peeker
import numpy as np
import pandas as pd
import matplotlib.pyplot as plt
%matplotlib inline

from sympy import *
init_printing()

import itertools

#EE drawing tools in python from https://cdelker.bitbucket.io/SchemDraw/
import SchemDraw as schem
import SchemDraw.elements as e
import SchemDraw.logic as l

#https://github.com/jrjohansson/version_information
%load_ext version_information
%version_information myhdl, myhdlpeek, numpy, pandas, matplotlib, sympy, itertools, SchemDraw


    

    
Out[1]:




Software
Version
Python
3.6.2 64bit [GCC 4.4.7 20120313 (Red Hat 4.4.7-1)]
IPython
6.2.1
OS
Linux 4.15.0 30 generic x86_64 with debian stretch sid
myhdl
0.10
myhdlpeek
0.0.6
numpy
1.13.3
pandas
0.23.3
matplotlib
2.1.0
sympy
1.1.2.dev
itertools
The 'itertools' distribution was not found and is required by the application
SchemDraw
0.3.0
Mon Sep 03 14:42:23 2018 MDT

In [2]:

    

#helper  functions to read in the .v and .vhd generated files into python
def VerilogTextReader(loc, printresult=True):
    with open(f'{loc}.v', 'r') as vText:
        VerilogText=vText.read()
    if printresult:
        print(f'***Verilog modual from {loc}.v***\n\n', VerilogText)
    return VerilogText

def VHDLTextReader(loc, printresult=True):
    with open(f'{loc}.vhd', 'r') as vText:
        VerilogText=vText.read()
    if printresult:
        print(f'***VHDL modual from {loc}.vhd***\n\n', VerilogText)
    return VerilogText

def ConstraintXDCTextReader(loc, printresult=True):
    with open(f'{loc}.xdc', 'r') as xdcText:
        ConstraintText=xdcText.read()
    if printresult:
        print(f'***Constraint file from {loc}.xdc***\n\n', ConstraintText)
    return ConstraintText


    

In [3]:

    

def TruthTabelGenrator(BoolSymFunc):
    """
    Function to generate a truth table from a sympy boolian expression
    BoolSymFunc: sympy boolian expression
    return TT: a Truth table stored in a pandas dataframe
    """
    colsL=sorted([i for i in list(BoolSymFunc.rhs.atoms())], key=lambda x:x.sort_key())
    colsR=sorted([i for i in list(BoolSymFunc.lhs.atoms())], key=lambda x:x.sort_key())
    bitwidth=len(colsL)
    cols=colsL+colsR; cols
    
    TT=pd.DataFrame(columns=cols, index=range(2**bitwidth))
    
    for i in range(2**bitwidth):
        inputs=[int(j) for j in list(np.binary_repr(i, bitwidth))]
        outputs=BoolSymFunc.rhs.subs({j:v for j, v in zip(colsL, inputs)})
        inputs.append(int(bool(outputs)))
        TT.iloc[i]=inputs
    
    return TT


    

In [4]:

    

d = schem.Drawing(unit=.5)
d.add(e.VDD, label='High')
d.add(e.LINE, l=d.unit*2, d='down')
d.add(e.DOT_OPEN, botlabel='$1$')
d.draw()


    

In [5]:

    

Y=symbols('Y')
YEq=Eq(Y, 1); YEq


    

    
Out[5]:





$$Y = 1$$

In [6]:

    

#decorator to specify a myHDL module that can be converted
#to myHDL
@block
def WireHigh(Y):
    """
    Wire to Constatnt High
    Input:
        None
    Output:
        Y(bool): output
    """
    #create signal to High Source
    HSource=Signal(bool(1))
    
    #decorator for a compintorical senstvity
    @always_comb
    def logic():
        #internal function to specfiy Out is set to High Source
        Y.next=HSource
    
    #return all internal functions
    return instances()


    

In [7]:

    

#create output signal to bind to `WireHigh` Mod
Y=Signal(bool(0))
#Create instatnce of `WireHigh` and bind `Out` Signal to it
DUT=WireHigh(Y)
#Run convert on `DUT` instance of `WireHigh` to create Verilog/VHDL
DUT.convert()
#Read ouput `WireHigh.v` into notebook
VerilogTextReader('WireHigh');


    

    




***Verilog modual from WireHigh.v***

 // File: WireHigh.v
// Generated by MyHDL 0.10
// Date: Mon Sep  3 14:42:38 2018


`timescale 1ns/10ps

module WireHigh (
    Y
);
// Wire to Constatnt High
// Input:
//     None
// Output:
//     Y(bool): output

output Y;
wire Y;

wire HSource;

assign HSource = 1'd1;



assign Y = HSource;

endmodule







    




/home/iridium/anaconda3/lib/python3.6/site-packages/myhdl/conversion/_toVerilog.py:349: ToVerilogWarning: Signal is not driven: HSource
  category=ToVerilogWarning

In [8]:

    

d = schem.Drawing(unit=.5)
d.add(e.VDD, label='High')
d.add(e.LINE, l=d.unit*2, d='down')
d.add(e.DOT, rgtlabel='$1$')
d.add(e.LINE, d='down', l=d.unit*2)
d.add(e.LED, rgtlabel='LD0', d='down')

#LED to ground
d.add(e.LINE, d='down', l=d.unit*1.5)
d.add(e.GND)
d.draw()


    

In [9]:

    

ConstraintXDCTextReader('PYNQ_Z1Constraints_WireHigh');


    

    




***Constraint file from PYNQ_Z1Constraints_WireHigh.xdc***

 ## PYNQ-Z1 Board Constraints for WireHigh.v
## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-Master.xdc

##LED 0
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {Y}]

In [10]:

    

d = schem.Drawing(unit=.5)
d.add(e.DOT_OPEN, label='$0$')
d.add(e.LINE, l=d.unit*2, d='down')
d.add(e.GND)
d.draw()


    

In [11]:

    

Y=Symbol('Y')
YEq=Eq(Y, 0); YEq


    

    
Out[11]:





$$Y = 0$$

In [12]:

    

#decorator to specify a myHDL module that can be converted
#to myHDL
@block
def WireLow(Y):
    """
    Wire to Constatnt Low
    Input:
        None
    Output:
        Y(bool): output
    """
    #create signal to Low Source
    LSource=Signal(bool(0))
    
    #decorator for a compintorical senstvity
    @always_comb
    def logic():
        #internal function to specfiy Out is set to Low Source
        Y.next=LSource
    
    #return all internal functions
    return instances()


    

In [13]:

    

#create output signal to bind to `WireHigh` Mod
Y=Signal(bool(0))
#Create instatnce of `WireHigh` and bind `Out` Signal to it
DUT=WireLow(Y)
#Run convert on `DUT` instance of `WireHigh` to create Verilog/VHDL
DUT.convert()
#Read ouput `WireHigh.v` into notebook
VerilogTextReader('WireLow');


    

    




***Verilog modual from WireLow.v***

 // File: WireLow.v
// Generated by MyHDL 0.10
// Date: Mon Sep  3 14:43:08 2018


`timescale 1ns/10ps

module WireLow (
    Y
);
// Wire to Constatnt Low
// Input:
//     None
// Output:
//     Y(bool): output

output Y;
wire Y;

wire LSource;

assign LSource = 1'd0;



assign Y = LSource;

endmodule







    




/home/iridium/anaconda3/lib/python3.6/site-packages/myhdl/conversion/_toVerilog.py:349: ToVerilogWarning: Signal is not driven: LSource
  category=ToVerilogWarning

In [14]:

    

d = schem.Drawing(unit=.5)
LD0=d.add(e.LED, d='right', label='LD0')
d.add(e.LINE, l=d.unit*2, d='left', xy=LD0.start)
d.add(e.LINE, l=d.unit*2, d='down')
d.add(e.GND)

d.add(e.LINE, l=d.unit*2, d='right', xy=LD0.end)
d.add(e.LINE, l=d.unit*2, d='down')
d.add(e.GND)
d.draw()


    

In [15]:

    

ConstraintXDCTextReader('PYNQ_Z1Constraints_WireLow');


    

    




***Constraint file from PYNQ_Z1Constraints_WireLow.xdc***

 ## PYNQ-Z1 Board Constraints for WireHigh.v
## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-Master.xdc

##LED 0
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {Y}]

In [16]:

    

d = schem.Drawing(unit=.5)
d.add(e.DOT_OPEN, l=d.unit*3, lftlabel='$X$')
d.add(l.BUF, label='$Buffer$')
d.add(e.DOT_OPEN, l=d.unit*2, rgtlabel='$Y$')
d.draw()


    

In [17]:

    

X, Y=symbols('X, Y')
YEq=Eq(Y, X); YEq


    

    
Out[17]:





$$Y = X$$

In [18]:

    

TruthTabelGenrator(YEq)


    

    
Out[18]:







  

    

      

      
X
      
Y
    
  
  

    

      
0
      
0
      
0
    
    

      
1
      
1
      
1
    
  

In [19]:

    

#convert the Sympy exspresion to a 
#numpy exspresion via lambdify
YEqN=lambdify(X, YEq.rhs, dummify=False)
YEqN(np.array([0, 1]))


    

    
Out[19]:





array([0, 1])

In [20]:

    

@block
def BufferGate(X, Y):
    """
    Buffer Gate demo module
    Input:
        X(bool): Input conection to wire between `X` and `Y`
    Ouput:
        Y(bool): Output connection to wire between 'X' and 'Y'
    """
    @always_comb
    def logic():
        Y.next=X
    return instances()


    

In [21]:

    

#generate random test values for BufferGate_TB
#stimules input In
TestLen=10
#for testing purpose the random genrator need to be seeded
#to create reproducable values
np.random.seed(12)
XTVs=np.random.randint(0,2, TestLen).astype(int)
XTVs


    

    
Out[21]:





array([1, 1, 0, 1, 1, 0, 1, 1, 0, 0])

In [22]:

    

#clear any previouse stored values in Peeker
Peeker.clear()
#Create the Signals to the BufferGate and 
#add them to Peeker for display and anylis
X=Signal(bool(0)); Peeker(X, 'X')
Y=Signal(bool(0)); Peeker(Y, 'Y')

#create instance of `BufferGate` and bind signals
#to it as the "Device Under Testing"
DUT=BufferGate(X, Y)

#Create a Testbench for `BufferGate`
def BufferGate_TB():
    """
    myHDL only testbench for module `BufferGate`
    """
    #internal function that will apply
    #stimules to DUT 
    @instance
    def stimules():
        for i in range(TestLen):
            #asign next stimules value to X input of DUT
            #for every 1 interval delay
            X.next=int(XTVs[i])
            yield delay(1)
        
        #flag to end the simulation of the DUT after all
        #stimules have been run
        raise StopSimulation()
    
    #return all internal stimules
    return instances()

#bind the DUT, Testbench and Peeker to simulator and run it
sim=Simulation(DUT, BufferGate_TB(), *Peeker.instances()).run()


    

In [23]:

    

#View Waveform diagram from Simulation with
#wavefroms in the order of `X` then `Y`
Peeker.to_wavedrom('X', 'Y')


    

In [24]:

    

#Capture the Waveform as a Pandas Dataframe for
#detiled anylsis
WireData=Peeker.to_dataframe()
#order the cols in the dataframe `X` then `Y`
WireData=WireData[['X', 'Y']]
WireData


    

    
Out[24]:







  

    

      

      
X
      
Y
    
  
  

    

      
0
      
1
      
1
    
    

      
2
      
0
      
0
    
    

      
3
      
1
      
1
    
    

      
5
      
0
      
0
    
    

      
6
      
1
      
1
    
    

      
8
      
0
      
0
    
  

In [25]:

    

#apply the lampdfid sympy expspresion for a buffer to the X input to
#get a refrance to compare the BufferGate modules 
WireData['YRef']=WireData['X'].apply(YEqN)
WireData


    

    
Out[25]:







  

    

      

      
X
      
Y
      
YRef
    
  
  

    

      
0
      
1
      
1
      
1
    
    

      
2
      
0
      
0
      
0
    
    

      
3
      
1
      
1
      
1
    
    

      
5
      
0
      
0
      
0
    
    

      
6
      
1
      
1
      
1
    
    

      
8
      
0
      
0
      
0
    
  

In [26]:

    

#Test wither the modules ouput matchs the sympy refrance
Test=(WireData['Y']==WireData['YRef']).all()
print(f'Module `BufferGate` works as exspected: {Test}')


    

    




Module `BufferGate` works as exspected: True

In [27]:

    

DUT.convert()
VerilogTextReader('BufferGate');


    

    




***Verilog modual from BufferGate.v***

 // File: BufferGate.v
// Generated by MyHDL 0.10
// Date: Mon Sep  3 14:43:49 2018


`timescale 1ns/10ps

module BufferGate (
    X,
    Y
);
// Buffer Gate demo module
// Input:
//     X(bool): Input conection to wire between `X` and `Y`
// Ouput:
//     Y(bool): Output connection to wire between 'X' and 'Y'

input X;
output Y;
wire Y;





assign Y = X;

endmodule

In [28]:

    

#create BitVector for BufferGate_TBV
XTVs=intbv(int(''.join(XTVs.astype(str)), 2))[TestLen:]
XTVs, bin(XTVs)


    

    
Out[28]:





(intbv(876), '1101101100')

In [29]:

    

#Convertable testbenchs must be treated as a module
@block
def BufferGate_TBV():
    """
    myHDL -> Verilog testbench for module `BufferGate`
    """
    #create the signals to bind to the DUT
    X=Signal(bool(0))
    Y=Signal(bool(0))
    
    #print out the waveform of `X` and `Y`
    @always_comb
    def print_data():
        print(X, Y)
    
    #create a register to hold the testdata vector
    #Test Signal Bit Vector
    XTV=Signal(XTVs)
    
    #create an instance of the `BufferGate` and
    #bind X and Y to it
    DUT=BufferGate(X, Y)
    
    #create the stimules action
    @instance
    def stimules():
        for i in range(TestLen):
            #asign X the next bit from XTV testvector reg
            X.next=XTV[i]
            #delay one of the smallest time intervals
            yield delay(1)
        
        #raise the stop simulation flag
        raise StopSimulation()
    
    #return all internals of the Testbench
    return instances()

#create instance of the Testbench
TB=BufferGate_TBV()
#run the conversion to Verilog and insure that
#all Signal values are at there default value
TB.convert(hdl="Verilog", initial_values=True)
#read back the testbench into python
VerilogTextReader('BufferGate_TBV');


    

    




<class 'myhdl._Signal._Signal'> <class '_ast.Name'>
<class 'myhdl._Signal._Signal'> <class '_ast.Name'>
***Verilog modual from BufferGate_TBV.v***

 // File: BufferGate_TBV.v
// Generated by MyHDL 0.10
// Date: Mon Sep  3 14:43:59 2018


`timescale 1ns/10ps

module BufferGate_TBV (

);
// myHDL -> Verilog testbench for module `BufferGate`


wire Y;
reg X = 0;
wire [9:0] XTV;

assign XTV = 10'd876;


always @(X, Y) begin: BUFFERGATE_TBV_PRINT_DATA
    $write("%h", X);
    $write(" ");
    $write("%h", Y);
    $write("\n");
end



assign Y = X;


initial begin: BUFFERGATE_TBV_STIMULES
    integer i;
    for (i=0; i<10; i=i+1) begin
        X <= XTV[i];
        # 1;
    end
    $finish;
end

endmodule







    




/home/iridium/anaconda3/lib/python3.6/site-packages/myhdl/conversion/_toVerilog.py:349: ToVerilogWarning: Signal is not driven: XTV
  category=ToVerilogWarning

In [30]:

    

d=schem.Drawing(unit=.5)
#add switch
SW0=d.add(e.SWITCH_SPDT2, reverse=True, label='SW0')

#connect to buffer
d.add(e.LINE, d='right', xy=SW0.a, l=d.unit*2, label='X')
d.add(e.DOT)
B0=d.add(l.BUF, label='BUF')

#buffer to LED
d.add(e.DOT)
d.add(e.LINE, d='right', l=d.unit*2, label='Y')
d.add(e.LINE, d='down', l=d.unit*2)
d.add(e.LED, rgtlabel='LD0', d='down')

#LED to ground
d.add(e.LINE, d='down', l=d.unit*1.5)
d.add(e.GND)

#swtich bottom to ground
d.add(e.LINE, d='down', xy=SW0.c, l=d.unit*4)
d.add(e.GND)


#switch top to rail
d.add(e.LINE, d='up', xy=SW0.b, l=d.unit*2.3)
d.add(e.VDD)
d.draw()


    

In [31]:

    

ConstraintXDCTextReader('PYNQ_Z1Constraints_BufferGate');


    

    




***Constraint file from PYNQ_Z1Constraints_BufferGate.xdc***

 ## PYNQ-Z1 Board Constraints for BufferGate.v
## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-Master.xdc


## Switch 0
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {X}]


##LED 0
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {Y}]

In [32]:

    

d = schem.Drawing(unit=.5)
d.add(e.DOT_OPEN, l=d.unit*3, lftlabel='$X$')
d.add(l.NOT, label='$NOT$')
d.add(e.LINE)
d.add(e.DOT_OPEN, rgtlabel='$Y$')
d.draw()


    

In [33]:

    

X, Y=symbols('X, Y')
YEq=Eq(Y, ~X); YEq


    

    
Out[33]:





$$Y = \neg X$$

In [34]:

    

TruthTabelGenrator(YEq)


    

    
Out[34]:







  

    

      

      
X
      
Y
    
  
  

    

      
0
      
0
      
1
    
    

      
1
      
1
      
0
    
  

In [35]:

    

YEqN=lambdify(X, YEq.rhs, dummify=False)
YEqN(0), YEqN(1)


    

    
Out[35]:





(True, False)

In [36]:

    

@block
def NotGate(X, Y):
    """
    NOT gate exsample module
    
    Input:
        X(bool): input
    
    Output:
        Y(bool): ouput
    
    """
    @always_comb
    def logic():
        Y.next=not X
        
    return instances()


    

In [37]:

    

#generate random test values for NotGate_TB
#stimules input In
TestLen=10
np.random.seed(14)
XTVs=np.random.randint(0,2, TestLen).astype(int)
XTVs


    

    
Out[37]:





array([1, 0, 0, 0, 1, 1, 0, 0, 0, 0])

In [38]:

    

Peeker.clear()
X=Signal(bool(0)); Peeker(X, 'X')
Y=Signal(bool(0)); Peeker(Y, 'Y')

DUT=NotGate(X, Y)

def NotGate_TB():
    """
    myHDL only testbench for module `NotGate`
    """
    
    @instance
    def stimules():
        for i in range(TestLen):
            X.next=int(XTVs[i])
            yield delay(1)
        
        raise StopSimulation()
        
    return instances()

sim=Simulation(DUT, NotGate_TB(), *Peeker.instances()).run()


    

In [39]:

    

Peeker.to_wavedrom()


    

In [40]:

    

NotData=Peeker.to_dataframe()
NotData


    

    
Out[40]:







  

    

      

      
X
      
Y
    
  
  

    

      
0
      
1
      
0
    
    

      
1
      
0
      
1
    
    

      
4
      
1
      
0
    
    

      
6
      
0
      
1
    
  

In [41]:

    

NotData['YRef']=NotData['X'].apply(YEqN).astype(int)
NotData


    

    
Out[41]:







  

    

      

      
X
      
Y
      
YRef
    
  
  

    

      
0
      
1
      
0
      
0
    
    

      
1
      
0
      
1
      
1
    
    

      
4
      
1
      
0
      
0
    
    

      
6
      
0
      
1
      
1
    
  

In [42]:

    

Test=(NotData['Y']==NotData['YRef']).all()
print(f'Module `NotGate` works as exspected: {Test}')


    

    




Module `NotGate` works as exspected: True

In [43]:

    

DUT.convert()
VerilogTextReader('NotGate');


    

    




***Verilog modual from NotGate.v***

 // File: NotGate.v
// Generated by MyHDL 0.10
// Date: Mon Sep  3 14:44:38 2018


`timescale 1ns/10ps

module NotGate (
    X,
    Y
);
// NOT gate exsample module
// 
// Input:
//     X(bool): input
// 
// Output:
//     Y(bool): ouput

input X;
output Y;
wire Y;





assign Y = (!X);

endmodule

In [44]:

    

#create BitVector for NotGate_TBV
XTVs=intbv(int(''.join(XTVs.astype(str)), 2))[TestLen:]
XTVs, bin(XTVs)


    

    
Out[44]:





(intbv(560), '1000110000')

In [45]:

    

@block
def NotGate_TBV():
    """
    myHDL -> Verilog testbench for module `NotGate`
    """
    X=Signal(bool(0))
    Y=Signal(bool(0))
    
    @always_comb
    def print_data():
        print(X, Y)
    
    #Test Signal Bit Vector
    XTV=Signal(XTVs)

    DUT=NotGate(X, Y)


    @instance
    def stimules():
        for i in range(TestLen):
            X.next=XTV[i]
            yield delay(1)
        
        raise StopSimulation()
    return instances()

TB=NotGate_TBV()
TB.convert(hdl="Verilog", initial_values=True)
VerilogTextReader('NotGate_TBV');


    

    




<class 'myhdl._Signal._Signal'> <class '_ast.Name'>
<class 'myhdl._Signal._Signal'> <class '_ast.Name'>
***Verilog modual from NotGate_TBV.v***

 // File: NotGate_TBV.v
// Generated by MyHDL 0.10
// Date: Mon Sep  3 14:44:48 2018


`timescale 1ns/10ps

module NotGate_TBV (

);
// myHDL -> Verilog testbench for module `NotGate`


wire Y;
reg X = 0;
wire [9:0] XTV;

assign XTV = 10'd560;


always @(X, Y) begin: NOTGATE_TBV_PRINT_DATA
    $write("%h", X);
    $write(" ");
    $write("%h", Y);
    $write("\n");
end



assign Y = (!X);


initial begin: NOTGATE_TBV_STIMULES
    integer i;
    for (i=0; i<10; i=i+1) begin
        X <= XTV[i];
        # 1;
    end
    $finish;
end

endmodule







    




/home/iridium/anaconda3/lib/python3.6/site-packages/myhdl/conversion/_toVerilog.py:349: ToVerilogWarning: Signal is not driven: XTV
  category=ToVerilogWarning

In [46]:

    

d=schem.Drawing(unit=.5)
#add switch
SW0=d.add(e.SWITCH_SPDT2, reverse=True, label='SW0')

#connect to buffer
d.add(e.LINE, d='right', xy=SW0.a, l=d.unit*2, label='X')
d.add(e.DOT)
N0=d.add(l.NOT, label='NOT')

#buffer to LED
d.add(e.DOT)
d.add(e.LINE, d='right', l=d.unit*2, label='Y')
d.add(e.LINE, d='down', l=d.unit*2)
d.add(e.LED, rgtlabel='LD0', d='down')

#LED to ground
d.add(e.LINE, d='down', l=d.unit*1.5)
d.add(e.GND)

#swtich bottom to ground
d.add(e.LINE, d='down', xy=SW0.c, l=d.unit*4)
d.add(e.GND)


#switch top to rail
d.add(e.LINE, d='up', xy=SW0.b, l=d.unit*2.3)
d.add(e.VDD)
d.draw()


    

In [47]:

    

ConstraintXDCTextReader('PYNQ_Z1Constraints_NotGate');


    

    




***Constraint file from PYNQ_Z1Constraints_NotGate.xdc***

 ## PYNQ-Z1 Board Constraints for NotGate.v
## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-Master.xdc


## Switch 0
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {X}]


##LED 0
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {Y}]

In [48]:

    

d = schem.Drawing(unit=.5)
G = d.add(l.AND2, label='$AND_2$')
d.add(e.DOT_OPEN, xy=G.out, rgtlabel='$Y$')
d.add(e.DOT_OPEN, xy=G.in1, lftlabel='$X_1$')
d.add(e.DOT_OPEN, xy=G.in2, lftlabel='$X_0$')
d.draw()


    

In [49]:

    

X0, X1, Y=symbols('X_0, X_1, Y')
YEq=Eq(Y, X0&X1); YEq


    

    
Out[49]:





$$Y = X_{0} \wedge X_{1}$$

In [50]:

    

TruthTabelGenrator(YEq)


    

    
Out[50]:







  

    

      

      
X_0
      
X_1
      
Y
    
  
  

    

      
0
      
0
      
0
      
0
    
    

      
1
      
0
      
1
      
0
    
    

      
2
      
1
      
0
      
0
    
    

      
3
      
1
      
1
      
1
    
  

In [51]:

    

YEqN=lambdify([X0, X1], YEq.rhs, dummify=False)
SystmaticVals=np.array(list(itertools.product([0,1], repeat=2)))
SystmaticVals, YEqN(SystmaticVals[:, 1], SystmaticVals[:, 0]).astype(int)


    

    
Out[51]:





(array([[0, 0],
        [0, 1],
        [1, 0],
        [1, 1]]), array([0, 0, 0, 1]))

In [52]:

    

@block
def AndGate(X0, X1, Y):
    """
    And Gate demo module
    
    Input:
        X0(bool): And gate input 0
        X1(bool): And gate input 1
    
    Output:
        Y(bool): And gate ouput 
    
    """
    @always_comb
    def logic():
        #note here that `and` is used since this
        #is a bit wise AND 
        Y.next=X0 and X1
        
        #if `&` had been used the conversion 
        #would yield `&` the .all() AND
        # when dealing with bus's and  behavior mux's this
        #distiction must be known
        #see:
        # https://stackoverflow.com/questions/17327680/what-is-the-difference-between-single-and-double-ampersand-binary-opera
    
    return instances()


    

In [53]:

    

#generate systmatic and random test values for AndGate_TB
#stimules inputs X1 and X2
TestLen=10
SystmaticVals=list(itertools.product([0,1], repeat=2))
X0TVs=np.array([i[1] for i in SystmaticVals]).astype(int)
np.random.seed(15)
X0TVs=np.append(X0TVs, np.random.randint(0,2, TestLen)).astype(int)

X1TVs=np.array([i[0] for i in SystmaticVals]).astype(int)
#the random genrator must have a differint seed beween each generation
#call in order to produce differint values for each call
np.random.seed(16)
X1TVs=np.append(X1TVs, np.random.randint(0,2, TestLen)).astype(int)

TestLen=len(X1TVs)
SystmaticVals, X1TVs, X0TVs, TestLen


    

    
Out[53]:





([(0, 0), (0, 1), (1, 0), (1, 1)],
 array([0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0]),
 array([0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 1]),
 14)

In [54]:

    

Peeker.clear()
X0=Signal(bool(0)); Peeker(X0, 'X0')
X1=Signal(bool(0)); Peeker(X1, 'X1')
Y=Signal(bool(0)); Peeker(Y, 'Y')

DUT=AndGate(X0, X1, Y)

def AndGate_TB():
    """
    myHDL only testbench for module `AndGate`
    """
    
    @instance
    def stimules():
        for i in range(TestLen):
            X0.next=int(X0TVs[i])
            X1.next=int(X1TVs[i])
            yield delay(1)
        
        raise StopSimulation()
        
    return instances()

sim=Simulation(DUT, AndGate_TB(), *Peeker.instances()).run()


    

In [55]:

    

Peeker.to_wavedrom('X1', 'X0', 'Y')


    

In [56]:

    

AndData=Peeker.to_dataframe()
AndData=AndData[['X1', 'X0', 'Y']]
AndData


    

    
Out[56]:







  

    

      

      
X1
      
X0
      
Y
    
  
  

    

      
0
      
0
      
0
      
0
    
    

      
1
      
0
      
1
      
0
    
    

      
2
      
1
      
0
      
0
    
    

      
3
      
1
      
1
      
1
    
    

      
4
      
1
      
0
      
0
    
    

      
5
      
0
      
1
      
0
    
    

      
6
      
1
      
0
      
0
    
    

      
7
      
1
      
1
      
1
    
    

      
9
      
1
      
0
      
0
    
    

      
10
      
0
      
0
      
0
    
    

      
11
      
1
      
1
      
1
    
    

      
13
      
0
      
1
      
0
    
  

In [57]:

    

AndData['YRef']=AndData.apply(lambda row:YEqN(row['X0'], row['X1']), axis=1).astype(int)
AndData


    

    
Out[57]:







  

    

      

      
X1
      
X0
      
Y
      
YRef
    
  
  

    

      
0
      
0
      
0
      
0
      
0
    
    

      
1
      
0
      
1
      
0
      
0
    
    

      
2
      
1
      
0
      
0
      
0
    
    

      
3
      
1
      
1
      
1
      
1
    
    

      
4
      
1
      
0
      
0
      
0
    
    

      
5
      
0
      
1
      
0
      
0
    
    

      
6
      
1
      
0
      
0
      
0
    
    

      
7
      
1
      
1
      
1
      
1
    
    

      
9
      
1
      
0
      
0
      
0
    
    

      
10
      
0
      
0
      
0
      
0
    
    

      
11
      
1
      
1
      
1
      
1
    
    

      
13
      
0
      
1
      
0
      
0
    
  

In [58]:

    

Test=(AndData['Y']==AndData['YRef']).all()
print(f'Module `AndGate` works as exspected: {Test}')


    

    




Module `AndGate` works as exspected: True

In [59]:

    

DUT.convert()
VerilogTextReader('AndGate');


    

    




***Verilog modual from AndGate.v***

 // File: AndGate.v
// Generated by MyHDL 0.10
// Date: Mon Sep  3 14:45:30 2018


`timescale 1ns/10ps

module AndGate (
    X0,
    X1,
    Y
);
// And Gate demo module
// 
// Input:
//     X0(bool): And gate input 0
//     X1(bool): And gate input 1
// 
// Output:
//     Y(bool): And gate ouput 

input X0;
input X1;
output Y;
wire Y;





assign Y = (X0 && X1);

endmodule

In [60]:

    

#create BitVectora for AndGate_TBV
X0TVs=intbv(int(''.join(X0TVs.astype(str)), 2))[TestLen:]
X1TVs=intbv(int(''.join(X1TVs.astype(str)), 2))[TestLen:]
X0TVs, bin(X0TVs), X1TVs, bin(X1TVs)


    

    
Out[60]:





(intbv(5479), '1010101100111', intbv(3830), '111011110110')

In [61]:

    

@block
def AndGate_TBV():
    """
    myHDL -> Verilog testbench for module `AndGate`
    """
    X0=Signal(bool(0))
    X1=Signal(bool(0))
    Y=Signal(bool(0))
    
    @always_comb
    def print_data():
        print(X0, X1, Y)
    
    #Test Signal Bit Vectors
    X0TV=Signal(X0TVs)
    X1TV=Signal(X1TVs)

    DUT=AndGate(X0, X1, Y)

    @instance
    def stimules():
        for i in range(TestLen):
            X0.next=int(X0TV[i])
            X1.next=int(X1TV[i])
            yield delay(1)
        
        raise StopSimulation()
    return instances()

TB=AndGate_TBV()
TB.convert(hdl="Verilog", initial_values=True)
VerilogTextReader('AndGate_TBV');


    

    




<class 'myhdl._Signal._Signal'> <class '_ast.Name'>
<class 'myhdl._Signal._Signal'> <class '_ast.Name'>
<class 'myhdl._Signal._Signal'> <class '_ast.Name'>
***Verilog modual from AndGate_TBV.v***

 // File: AndGate_TBV.v
// Generated by MyHDL 0.10
// Date: Mon Sep  3 14:45:40 2018


`timescale 1ns/10ps

module AndGate_TBV (

);
// myHDL -> Verilog testbench for module `AndGate`


wire Y;
reg X0 = 0;
reg X1 = 0;
wire [13:0] X0TV;
wire [13:0] X1TV;

assign X0TV = 14'd5479;
assign X1TV = 14'd3830;


always @(X1, Y, X0) begin: ANDGATE_TBV_PRINT_DATA
    $write("%h", X0);
    $write(" ");
    $write("%h", X1);
    $write(" ");
    $write("%h", Y);
    $write("\n");
end



assign Y = (X0 && X1);


initial begin: ANDGATE_TBV_STIMULES
    integer i;
    for (i=0; i<14; i=i+1) begin
        X0 <= X0TV[i];
        X1 <= X1TV[i];
        # 1;
    end
    $finish;
end

endmodule







    




/home/iridium/anaconda3/lib/python3.6/site-packages/myhdl/conversion/_toVerilog.py:349: ToVerilogWarning: Signal is not driven: X0TV
  category=ToVerilogWarning
/home/iridium/anaconda3/lib/python3.6/site-packages/myhdl/conversion/_toVerilog.py:349: ToVerilogWarning: Signal is not driven: X1TV
  category=ToVerilogWarning

In [62]:

    

d=schem.Drawing(unit=.5)
#add elements
G=d.add(l.AND2,d='right', label='$AND_2$')

#Gate to led to gnd

d.add(e.LINE, d='right', xy=G.out)
d.add(e.DOT, label='$Y$')
d.add(e.LINE, d='down', l=d.unit*2)
LD0=d.add(e.LED, d='down', label='LD0')
d.add(e.LINE, d='down', l=d.unit*2)
d.add(e.GND)

d.add(e.LINE, d='left', xy=G.in1, l=d.unit)
d.add(e.DOT, label='$X_0$')
d.add(e.LINE,d='left', l=d.unit)
d.add(e.LINE,d='up', l=d.unit*2)
d.add(e.LINE,d='left', l=d.unit*2)
SW0=d.add(e.SWITCH_SPDT, lftlabel='SW0')
d.add(e.GND, xy=SW0.c)
d.add(e.VDD, xy=SW0.b)


d.add(e.LINE, d='left', xy=G.in2, l=d.unit)
d.add(e.DOT, botlabel='$X_1$')
d.add(e.LINE,d='left', l=d.unit)
d.add(e.LINE,d='down', l=d.unit*2)
d.add(e.LINE,d='left', l=d.unit*4)
SW1=d.add(e.SWITCH_SPDT, lftlabel='SW1')
d.add(e.GND, xy=SW1.c)
d.add(e.VDD, xy=SW1.b)
d.draw()


    

In [63]:

    

ConstraintXDCTextReader('PYNQ_Z1Constraints_AndGate');


    

    




***Constraint file from PYNQ_Z1Constraints_AndGate.xdc***

 ## PYNQ-Z1 Board Constraints for AndGate.v
## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-Master.xdc


## Switchs 0,1
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {X0}]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports {X1}]



##LED 0
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {Y}]

In [64]:

    

d = schem.Drawing(unit=.5)
G = d.add(l.AND2, label='$OR_2$')
d.add(e.DOT_OPEN, xy=G.out, rgtlabel='$Y$')
d.add(e.DOT_OPEN, xy=G.in1, lftlabel='$X_1$')
d.add(e.DOT_OPEN, xy=G.in2, lftlabel='$X_0$')
d.draw()


    

In [65]:

    

X0, X1, Y=symbols('X_0, X_1, Y')
YEq=Eq(Y, X0|X1); YEq


    

    
Out[65]:





$$Y = X_{0} \vee X_{1}$$

In [66]:

    

TruthTabelGenrator(YEq)


    

    
Out[66]:







  

    

      

      
X_0
      
X_1
      
Y
    
  
  

    

      
0
      
0
      
0
      
0
    
    

      
1
      
0
      
1
      
1
    
    

      
2
      
1
      
0
      
1
    
    

      
3
      
1
      
1
      
1
    
  

In [67]:

    

YEqN=lambdify([X0, X1], YEq.rhs, dummify=False)
SystmaticVals=np.array(list(itertools.product([0,1], repeat=2)))
SystmaticVals, YEqN(SystmaticVals[:, 1], SystmaticVals[:, 0]).astype(int)


    

    
Out[67]:





(array([[0, 0],
        [0, 1],
        [1, 0],
        [1, 1]]), array([0, 1, 1, 1]))

In [68]:

    

@block
def OrGate(X0, X1, Y):
    """
    Or Gate demo module
    
    Input:
        X0(bool): Or gate input 0
        X1(bool): Or gate input 1
    
    Output:
        Y(bool): Or gate ouput 
    
    """
    @always_comb
    def logic():
        #note here that `or` is used since this
        #is a bit wise OR 
        Y.next=X0 or X1
        
        #if `|` had been used the conversion 
        #would yield `||` the .all() OR
        # when dealing with bus's and  behavior mux's this
        #distiction must be known
        #see:
        # https://stackoverflow.com/questions/17327680/what-is-the-difference-between-single-and-double-ampersand-binary-opera
    
    return instances()


    

In [69]:

    

#generate systmatic and random test values for OrGate_TB
#stimules inputs X1 and X2
TestLen=10
SystmaticVals=list(itertools.product([0,1], repeat=2))
X0TVs=np.array([i[1] for i in SystmaticVals]).astype(int)
np.random.seed(17)
X0TVs=np.append(X0TVs, np.random.randint(0,2, TestLen)).astype(int)

X1TVs=np.array([i[0] for i in SystmaticVals]).astype(int)
np.random.seed(18)
X1TVs=np.append(X1TVs, np.random.randint(0,2, TestLen)).astype(int)

TestLen=len(X1TVs)
SystmaticVals, X1TVs, X0TVs, TestLen


    

    
Out[69]:





([(0, 0), (0, 1), (1, 0), (1, 1)],
 array([0, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0]),
 array([0, 1, 0, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 1]),
 14)

In [70]:

    

Peeker.clear()
X0=Signal(bool(0)); Peeker(X0, 'X0')
X1=Signal(bool(0)); Peeker(X1, 'X1')
Y=Signal(bool(0)); Peeker(Y, 'Y')

DUT=OrGate(X0, X1, Y)

def OrGate_TB():
    """
    myHDL only testbench for module `OrGate`
    """
    
    @instance
    def stimules():
        for i in range(TestLen):
            X0.next=int(X0TVs[i])
            X1.next=int(X1TVs[i])
            yield delay(1)
        
        raise StopSimulation()
        
    return instances()

sim=Simulation(DUT, OrGate_TB(), *Peeker.instances()).run()


    

In [71]:

    

Peeker.to_wavedrom('X1', 'X0', 'Y')


    

In [72]:

    

OrData=Peeker.to_dataframe()
OrData=OrData[['X1', 'X0', 'Y']]
OrData


    

    
Out[72]:







  

    

      

      
X1
      
X0
      
Y
    
  
  

    

      
0
      
0
      
0
      
0
    
    

      
1
      
0
      
1
      
1
    
    

      
2
      
1
      
0
      
1
    
    

      
3
      
1
      
1
      
1
    
    

      
4
      
0
      
1
      
1
    
    

      
5
      
1
      
1
      
1
    
    

      
6
      
0
      
1
      
1
    
    

      
7
      
1
      
0
      
1
    
    

      
8
      
0
      
0
      
0
    
    

      
9
      
1
      
1
      
1
    
    

      
10
      
0
      
0
      
0
    
    

      
11
      
0
      
1
      
1
    
    

      
12
      
0
      
0
      
0
    
    

      
13
      
0
      
1
      
1
    
  

In [73]:

    

OrData['YRef']=OrData.apply(lambda row:YEqN(row['X0'], row['X1']), axis=1).astype(int)
OrData


    

    
Out[73]:







  

    

      

      
X1
      
X0
      
Y
      
YRef
    
  
  

    

      
0
      
0
      
0
      
0
      
0
    
    

      
1
      
0
      
1
      
1
      
1
    
    

      
2
      
1
      
0
      
1
      
1
    
    

      
3
      
1
      
1
      
1
      
1
    
    

      
4
      
0
      
1
      
1
      
1
    
    

      
5
      
1
      
1
      
1
      
1
    
    

      
6
      
0
      
1
      
1
      
1
    
    

      
7
      
1
      
0
      
1
      
1
    
    

      
8
      
0
      
0
      
0
      
0
    
    

      
9
      
1
      
1
      
1
      
1
    
    

      
10
      
0
      
0
      
0
      
0
    
    

      
11
      
0
      
1
      
1
      
1
    
    

      
12
      
0
      
0
      
0
      
0
    
    

      
13
      
0
      
1
      
1
      
1
    
  

In [74]:

    

Test=(OrData['Y']==OrData['YRef']).all()
print(f'Module `OrGate` works as exspected: {Test}')


    

    




Module `OrGate` works as exspected: True

In [75]:

    

DUT.convert()
VerilogTextReader('OrGate');


    

    




***Verilog modual from OrGate.v***

 // File: OrGate.v
// Generated by MyHDL 0.10
// Date: Mon Sep  3 14:46:15 2018


`timescale 1ns/10ps

module OrGate (
    X0,
    X1,
    Y
);
// Or Gate demo module
// 
// Input:
//     X0(bool): Or gate input 0
//     X1(bool): Or gate input 1
// 
// Output:
//     Y(bool): Or gate ouput 

input X0;
input X1;
output Y;
wire Y;





assign Y = (X0 || X1);

endmodule

In [76]:

    

#create BitVectora for OrGate_TBV
X0TVs=intbv(int(''.join(X0TVs.astype(str)), 2))[TestLen:]
X1TVs=intbv(int(''.join(X1TVs.astype(str)), 2))[TestLen:]
X0TVs, bin(X0TVs), X1TVs, bin(X1TVs)


    

    
Out[76]:





(intbv(6037), '1011110010101', intbv(3408), '110101010000')

In [77]:

    

@block
def OrGate_TBV():
    """
    myHDL -> Verilog testbench for module `OrGate`
    """
    X0=Signal(bool(0))
    X1=Signal(bool(0))
    Y=Signal(bool(0))
    
    @always_comb
    def print_data():
        print(X0, X1, Y)
    
    #Test Signal Bit Vectors
    X0TV=Signal(X0TVs)
    X1TV=Signal(X1TVs)

    DUT=OrGate(X0, X1, Y)

    @instance
    def stimules():
        for i in range(TestLen):
            X0.next=int(X0TV[i])
            X1.next=int(X1TV[i])
            yield delay(1)
        
        raise StopSimulation()
    return instances()

TB=OrGate_TBV()
TB.convert(hdl="Verilog", initial_values=True)
VerilogTextReader('OrGate_TBV');


    

    




<class 'myhdl._Signal._Signal'> <class '_ast.Name'>
<class 'myhdl._Signal._Signal'> <class '_ast.Name'>
<class 'myhdl._Signal._Signal'> <class '_ast.Name'>
***Verilog modual from OrGate_TBV.v***

 // File: OrGate_TBV.v
// Generated by MyHDL 0.10
// Date: Mon Sep  3 14:46:26 2018


`timescale 1ns/10ps

module OrGate_TBV (

);
// myHDL -> Verilog testbench for module `OrGate`


wire Y;
reg X0 = 0;
reg X1 = 0;
wire [13:0] X0TV;
wire [13:0] X1TV;

assign X0TV = 14'd6037;
assign X1TV = 14'd3408;


always @(X1, Y, X0) begin: ORGATE_TBV_PRINT_DATA
    $write("%h", X0);
    $write(" ");
    $write("%h", X1);
    $write(" ");
    $write("%h", Y);
    $write("\n");
end



assign Y = (X0 || X1);


initial begin: ORGATE_TBV_STIMULES
    integer i;
    for (i=0; i<14; i=i+1) begin
        X0 <= X0TV[i];
        X1 <= X1TV[i];
        # 1;
    end
    $finish;
end

endmodule







    




/home/iridium/anaconda3/lib/python3.6/site-packages/myhdl/conversion/_toVerilog.py:349: ToVerilogWarning: Signal is not driven: X0TV
  category=ToVerilogWarning
/home/iridium/anaconda3/lib/python3.6/site-packages/myhdl/conversion/_toVerilog.py:349: ToVerilogWarning: Signal is not driven: X1TV
  category=ToVerilogWarning

In [78]:

    

d=schem.Drawing(unit=.5)
#add elements
G=d.add(l.OR2,d='right', label='$OR_2$')

#Gate to led to gnd

d.add(e.LINE, d='right', xy=G.out)
d.add(e.DOT, label='$Y$')
d.add(e.LINE, d='down', l=d.unit*2)
LD0=d.add(e.LED, d='down', label='LD0')
d.add(e.LINE, d='down', l=d.unit*2)
d.add(e.GND)

d.add(e.LINE, d='left', xy=G.in1, l=d.unit)
d.add(e.DOT, label='$X_0$')
d.add(e.LINE,d='left', l=d.unit)
d.add(e.LINE,d='up', l=d.unit*2)
d.add(e.LINE,d='left', l=d.unit*2)
SW0=d.add(e.SWITCH_SPDT, lftlabel='SW0')
d.add(e.GND, xy=SW0.c)
d.add(e.VDD, xy=SW0.b)


d.add(e.LINE, d='left', xy=G.in2, l=d.unit)
d.add(e.DOT, botlabel='$X_1$')
d.add(e.LINE,d='left', l=d.unit)
d.add(e.LINE,d='down', l=d.unit*2)
d.add(e.LINE,d='left', l=d.unit*4)
SW1=d.add(e.SWITCH_SPDT, lftlabel='SW1')
d.add(e.GND, xy=SW1.c)
d.add(e.VDD, xy=SW1.b)
d.draw()


    

In [79]:

    

ConstraintXDCTextReader('PYNQ_Z1Constraints_OrGate');


    

    




***Constraint file from PYNQ_Z1Constraints_OrGate.xdc***

 ## PYNQ-Z1 Board Constraints for XorGate.v
## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-Master.xdc


## Switchs 0,1
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {X0}]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports {X1}]


##LED 0
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {Y}]

In [80]:

    

d = schem.Drawing(unit=.5)
G = d.add(l.XOR2, label='$XOR_2$')
d.add(e.DOT_OPEN, xy=G.out, rgtlabel='$Y$')
d.add(e.DOT_OPEN, xy=G.in1, lftlabel='$X_1$')
d.add(e.DOT_OPEN, xy=G.in2, lftlabel='$X_0$')
d.draw()


    

In [81]:

    

X0, X1, Y=symbols('X_0, X_1, Y')
YEq=Eq(Y, X0^X1); YEq


    

    
Out[81]:





$$Y = X_{0} \veebar X_{1}$$

In [82]:

    

TruthTabelGenrator(YEq)


    

    
Out[82]:







  

    

      

      
X_0
      
X_1
      
Y
    
  
  

    

      
0
      
0
      
0
      
0
    
    

      
1
      
0
      
1
      
1
    
    

      
2
      
1
      
0
      
1
    
    

      
3
      
1
      
1
      
0
    
  

In [83]:

    

#lampdfy must have maping manuly set from `Xor` to `np.bitwise_xor`
YEqN=lambdify([X0, X1], YEq.rhs, {'Xor':np.bitwise_xor}, dummify=False)
SystmaticVals=np.array(list(itertools.product([0,1], repeat=2)))
SystmaticVals, YEqN(SystmaticVals[:, 1], SystmaticVals[:, 0]).astype(int)


    

    
Out[83]:





(array([[0, 0],
        [0, 1],
        [1, 0],
        [1, 1]]), array([0, 1, 1, 0]))

In [84]:

    

@block
def XorGate(X0, X1, Y):
    """
    XOR Gate demo module
    
    Input:
        X0(bool): XOR gate input 0
        X1(bool): XOR gate input 1
    
    Output:
        Y(bool): XOR gate ouput 
    
    """
    @always_comb
    def logic():
        Y.next=X0 ^ X1
        
    return instances()