From page 438 in annotated K20P64M72SF1RM manual (MK20DX128 processor used on Teensy 3.1/3.2).

21.5.1 eDMA initialization

To initialize the eDMA:

1. Write to the CR if a configuration other than the default is desired.
   • e.g., set arbitration scheme to round-robin or fixed-priority.
2. Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired.
3. Enable error interrupts in the EEI register if so desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the ERQ register.
6. Request channel service via either:
   • Software: setting the TCDn_CSR[START]
   • Hardware: slave device asserting its eDMA peripheral request signal

After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The eDMA engine reads the entire TCD, including the TCD control and status fields, as shown in the following table, for the selected channel into its internal address path module. As the TCD is read, the first transfer is initiated on the internal bus, unless a configuration error is detected. Transfers from the source, as defined by TCDn_SADDR, to the destination, as defined by TCDn_DADDR, continue until the number of bytes specified by TCDn_NBYTES are transferred.

When the transfer is complete:

• The eDMA engine's local TCDn_SADDR, TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory
• Any minor loop channel linking is performed, if enabled

If the major loop is exhausted, further post processing executes, such as interrupts, major loop channel linking, and scatter/gather operations, if enabled.

Enable Request Register (DMA_ERQ)

• 16-bit register, one bit per DMA channel.
• Each bit controls whether or not the hardware request signal is enabled for the corresponding channel.
• SERQ (Set Enable ReEquest) and CERQ (Clear Enable ReEquest) registers provide memory mapped convenience interfaces for setting a bit for a channel without having to read-modify-write the entire DMA_ERQ.
  • 8-bit SERQ and 8-bit CERQ register for each DMA channel.
  • Can write up to 4 8-bit registers at once, with NOP bit to "skip" a spanned register where necessary.

Single transfer of 16 bytes

16 bytes from source with byte wide port to destination with 32-bit port (i.e., 4 bytes).

See page 441 in annotated K20P64M72SF1RM manual (MK20DX128 processor used on Teensy 3.1/3.2).

ADC_SC1A: ADC Status and Control Registers 1

Page 653.

• COCO: Conversion complete flag
• AIEN: Interrupt enable
• DIFF: Differential mode enable
• ADCH: 4 bits, Input channel select

ADC_CFG1: ADC Configuration Register 1

Page 656

• ADLPC: Low-power configuration
• ADIV: 2 bits, Clock divide select
  • 0: /1, 1: /2, 2: /4, 3: /8
• ADLSMP: Sample time configuration
  • 0: Short sample time, 1: Long sample time
• MODE: 2 bits, Conversion mode selection
  • 0: 8-bit, 1: 12-bit, 2: 10-bit, 3: 16-bit
• ADICLK: 2 bits, Input clock select
  • 0: Bus clock, 1: Bus clock/2, 2: Alternate clock (ALTCLK), 2: Asynchronous clock (ADACK)

ADC_CFG2: ADC Configuration Register 2

Page 658.

• MUXSEL: ADC mux select
  • 0: ADxxa channels selected, 1: ADxxb channels selected
• ADACKEN: Asynchronous clock output enable
• ADHSC: High-speed configuration
• ADLSTS: Long sample time select

ADC_SC2: Status and Control Register 2

Page 661.

• ADACT: Conversion active
• ADTRG: Conversion trigger select
  • 0: Software trigger, 1: Hardware trigger
• ACFE: Compare Function Enable
• ACFGT: Compare function greater than enable
• ACREN: Compare function range enable
• DMAEN: DMA enable
  • 1: 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
• REFSEL: 2 bits, Voltage reference selection
  • 0: Default, 1: Alternate, 2-3: Reserved

ADC_SC3: Status and Control Register 3

Page 663.

• CAL: Calibration
• CALF: Calibration failed flag
• ADCO: Continuous conversion enable
• AVGE: Hardware average enable
• AVGS: Hardware average select
  • Samples averaged - 0: 4, 1: 8, 0: 16, 0: 32

ADC_PGA: ADC PGA Register

Page 670.

• PGAEN: PGA enable
• PGALPb: PGA low-power mode control
• PGAG: 19-16, PGA Gain setting, $PGA~gain = 2^{PGAG}$
  • 0: 1, 1: 2, 2: 4, 3: 8, 4: 16, 5: 32, 6: 64