CoreIR

This notebook uses the "coreir" mantle backend on the icestick.

We begin by building a normal Magma circuit using Mantle and the Loam IceStick board.



In [1]:

    
import magma as m
# default mantle target is coreir, so no need to do this unless you want to be explicit
# m.set_mantle_target("coreir")



In [2]:

    
from mantle import Counter
from loam.boards.icestick import IceStick

icestick = IceStick()
icestick.Clock.on()
icestick.D5.on()

N = 22
main = icestick.main()

counter = Counter(N)
m.wire(counter.O[N-1], main.D5)

m.EndCircuit()









    



import lattice ice40

To compile to coreir, we simply set the output parameter to the m.compile command to "coreir".



In [3]:

    
m.compile("build/blink_coreir", main, output="coreir")

We can inspect the generated .json file.



In [4]:

    
%cat build/blink_coreir.json









    



{"top":"global.main",
"namespaces":{
  "global":{
    "modules":{
      "Add22_cout":{
        "type":["Record",[
          ["I0",["Array",22,"BitIn"]],
          ["I1",["Array",22,"BitIn"]],
          ["O",["Array",22,"Bit"]],
          ["COUT","Bit"]
        ]],
        "instances":{
          "bit_const_0_None":{
            "modref":"corebit.const",
            "modargs":{"value":["Bool",false]}
          },
          "coreir_add23_inst0":{
            "genref":"coreir.add",
            "genargs":{"width":["Int",23]}
          }
        },
        "connections":[
          ["coreir_add23_inst0.in0.22","bit_const_0_None.out"],
          ["coreir_add23_inst0.in1.22","bit_const_0_None.out"],
          ["self.I0.0","coreir_add23_inst0.in0.0"],
          ["self.I0.10","coreir_add23_inst0.in0.10"],
          ["self.I0.11","coreir_add23_inst0.in0.11"],
          ["self.I0.12","coreir_add23_inst0.in0.12"],
          ["self.I0.13","coreir_add23_inst0.in0.13"],
          ["self.I0.14","coreir_add23_inst0.in0.14"],
          ["self.I0.15","coreir_add23_inst0.in0.15"],
          ["self.I0.16","coreir_add23_inst0.in0.16"],
          ["self.I0.17","coreir_add23_inst0.in0.17"],
          ["self.I0.18","coreir_add23_inst0.in0.18"],
          ["self.I0.19","coreir_add23_inst0.in0.19"],
          ["self.I0.1","coreir_add23_inst0.in0.1"],
          ["self.I0.20","coreir_add23_inst0.in0.20"],
          ["self.I0.21","coreir_add23_inst0.in0.21"],
          ["self.I0.2","coreir_add23_inst0.in0.2"],
          ["self.I0.3","coreir_add23_inst0.in0.3"],
          ["self.I0.4","coreir_add23_inst0.in0.4"],
          ["self.I0.5","coreir_add23_inst0.in0.5"],
          ["self.I0.6","coreir_add23_inst0.in0.6"],
          ["self.I0.7","coreir_add23_inst0.in0.7"],
          ["self.I0.8","coreir_add23_inst0.in0.8"],
          ["self.I0.9","coreir_add23_inst0.in0.9"],
          ["self.I1.0","coreir_add23_inst0.in1.0"],
          ["self.I1.10","coreir_add23_inst0.in1.10"],
          ["self.I1.11","coreir_add23_inst0.in1.11"],
          ["self.I1.12","coreir_add23_inst0.in1.12"],
          ["self.I1.13","coreir_add23_inst0.in1.13"],
          ["self.I1.14","coreir_add23_inst0.in1.14"],
          ["self.I1.15","coreir_add23_inst0.in1.15"],
          ["self.I1.16","coreir_add23_inst0.in1.16"],
          ["self.I1.17","coreir_add23_inst0.in1.17"],
          ["self.I1.18","coreir_add23_inst0.in1.18"],
          ["self.I1.19","coreir_add23_inst0.in1.19"],
          ["self.I1.1","coreir_add23_inst0.in1.1"],
          ["self.I1.20","coreir_add23_inst0.in1.20"],
          ["self.I1.21","coreir_add23_inst0.in1.21"],
          ["self.I1.2","coreir_add23_inst0.in1.2"],
          ["self.I1.3","coreir_add23_inst0.in1.3"],
          ["self.I1.4","coreir_add23_inst0.in1.4"],
          ["self.I1.5","coreir_add23_inst0.in1.5"],
          ["self.I1.6","coreir_add23_inst0.in1.6"],
          ["self.I1.7","coreir_add23_inst0.in1.7"],
          ["self.I1.8","coreir_add23_inst0.in1.8"],
          ["self.I1.9","coreir_add23_inst0.in1.9"],
          ["self.O.0","coreir_add23_inst0.out.0"],
          ["self.O.10","coreir_add23_inst0.out.10"],
          ["self.O.11","coreir_add23_inst0.out.11"],
          ["self.O.12","coreir_add23_inst0.out.12"],
          ["self.O.13","coreir_add23_inst0.out.13"],
          ["self.O.14","coreir_add23_inst0.out.14"],
          ["self.O.15","coreir_add23_inst0.out.15"],
          ["self.O.16","coreir_add23_inst0.out.16"],
          ["self.O.17","coreir_add23_inst0.out.17"],
          ["self.O.18","coreir_add23_inst0.out.18"],
          ["self.O.19","coreir_add23_inst0.out.19"],
          ["self.O.1","coreir_add23_inst0.out.1"],
          ["self.O.20","coreir_add23_inst0.out.20"],
          ["self.O.21","coreir_add23_inst0.out.21"],
          ["self.COUT","coreir_add23_inst0.out.22"],
          ["self.O.2","coreir_add23_inst0.out.2"],
          ["self.O.3","coreir_add23_inst0.out.3"],
          ["self.O.4","coreir_add23_inst0.out.4"],
          ["self.O.5","coreir_add23_inst0.out.5"],
          ["self.O.6","coreir_add23_inst0.out.6"],
          ["self.O.7","coreir_add23_inst0.out.7"],
          ["self.O.8","coreir_add23_inst0.out.8"],
          ["self.O.9","coreir_add23_inst0.out.9"]
        ]
      },
      "Counter22_COUT":{
        "type":["Record",[
          ["O",["Array",22,"Bit"]],
          ["COUT","Bit"],
          ["CLK",["Named","coreir.clkIn"]]
        ]],
        "instances":{
          "Add22_cout_inst0":{
            "modref":"global.Add22_cout"
          },
          "const_1_22":{
            "genref":"coreir.const",
            "genargs":{"width":["Int",22]},
            "modargs":{"value":[["BitVector",22],"22'h000001"]}
          },
          "reg_P_inst0":{
            "genref":"coreir.reg",
            "genargs":{"width":["Int",22]},
            "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",22],"22'h000000"]}
          }
        },
        "connections":[
          ["self.COUT","Add22_cout_inst0.COUT"],
          ["reg_P_inst0.out","Add22_cout_inst0.I0"],
          ["const_1_22.out","Add22_cout_inst0.I1"],
          ["reg_P_inst0.in","Add22_cout_inst0.O"],
          ["self.CLK","reg_P_inst0.clk"],
          ["self.O","reg_P_inst0.out"]
        ]
      },
      "main":{
        "type":["Record",[
          ["D5","Bit"],
          ["CLKIN",["Named","coreir.clkIn"]]
        ]],
        "instances":{
          "Counter22_COUT_inst0":{
            "modref":"global.Counter22_COUT"
          }
        },
        "connections":[
          ["self.CLKIN","Counter22_COUT_inst0.CLK"],
          ["self.D5","Counter22_COUT_inst0.O.21"]
        ]
      }
    }
  }
}
}

We can use the coreir command line tool to generate verilog.



In [5]:

    
%%bash
coreir -i build/blink_coreir.json -o build/blink_coreir.v









    



/Users/hanrahan/git/coreir/src/binary/coreir.cpp:188 Running Runningvpasses
/Users/hanrahan/git/coreir/src/passes/transform/rungenerators.cpp:10 In Run Generators
/Users/hanrahan/git/coreir/src/passes/transform/rungenerators.cpp:26 Done running generators
/Users/hanrahan/git/coreir/src/binary/coreir.cpp:197 Running vpasses
/Users/hanrahan/git/coreir/src/binary/coreir.cpp:238 Modified?: No

And now we can inspect the generated verilog from coreir, notice that includes the verilog implementations of all the coreir primitives.



In [6]:

    
%cat build/blink_coreir.v









    



module coreir_reg #(parameter width = 1, parameter clk_posedge = 1, parameter init = 1) (input clk, input [width-1:0] in, output [width-1:0] out);
  reg [width-1:0] outReg=init;
  wire real_clk;
  assign real_clk = clk_posedge ? clk : ~clk;
  always @(posedge real_clk) begin
    outReg <= in;
  end
  assign out = outReg;
endmodule

module coreir_const #(parameter width = 1, parameter value = 1) (output [width-1:0] out);
  assign out = value;
endmodule

module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
  assign out = in0 + in1;
endmodule

module corebit_const #(parameter value = 1) (output out);
  assign out = value;
endmodule

module Add22_cout (output COUT, input [21:0] I0, input [21:0] I1, output [21:0] O);
wire bit_const_0_None_out;
wire [22:0] coreir_add23_inst0_out;
corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out));
coreir_add #(.width(23)) coreir_add23_inst0(.in0({bit_const_0_None_out,I0[21],I0[20],I0[19],I0[18],I0[17],I0[16],I0[15],I0[14],I0[13],I0[12],I0[11],I0[10],I0[9],I0[8],I0[7],I0[6],I0[5],I0[4],I0[3],I0[2],I0[1],I0[0]}), .in1({bit_const_0_None_out,I1[21],I1[20],I1[19],I1[18],I1[17],I1[16],I1[15],I1[14],I1[13],I1[12],I1[11],I1[10],I1[9],I1[8],I1[7],I1[6],I1[5],I1[4],I1[3],I1[2],I1[1],I1[0]}), .out(coreir_add23_inst0_out));
assign COUT = coreir_add23_inst0_out[22];
assign O = {coreir_add23_inst0_out[21],coreir_add23_inst0_out[20],coreir_add23_inst0_out[19],coreir_add23_inst0_out[18],coreir_add23_inst0_out[17],coreir_add23_inst0_out[16],coreir_add23_inst0_out[15],coreir_add23_inst0_out[14],coreir_add23_inst0_out[13],coreir_add23_inst0_out[12],coreir_add23_inst0_out[11],coreir_add23_inst0_out[10],coreir_add23_inst0_out[9],coreir_add23_inst0_out[8],coreir_add23_inst0_out[7],coreir_add23_inst0_out[6],coreir_add23_inst0_out[5],coreir_add23_inst0_out[4],coreir_add23_inst0_out[3],coreir_add23_inst0_out[2],coreir_add23_inst0_out[1],coreir_add23_inst0_out[0]};
endmodule

module Counter22_COUT (input CLK, output COUT, output [21:0] O);
wire Add22_cout_inst0_COUT;
wire [21:0] Add22_cout_inst0_O;
wire [21:0] const_1_22_out;
wire [21:0] reg_P_inst0_out;
Add22_cout Add22_cout_inst0(.COUT(Add22_cout_inst0_COUT), .I0(reg_P_inst0_out), .I1(const_1_22_out), .O(Add22_cout_inst0_O));
coreir_const #(.value(22'h000001), .width(22)) const_1_22(.out(const_1_22_out));
coreir_reg #(.clk_posedge(1), .init(22'h000000), .width(22)) reg_P_inst0(.clk(CLK), .in(Add22_cout_inst0_O), .out(reg_P_inst0_out));
assign COUT = Add22_cout_inst0_COUT;
assign O = reg_P_inst0_out;
endmodule

module main (input CLKIN, output D5);
wire Counter22_COUT_inst0_COUT;
wire [21:0] Counter22_COUT_inst0_O;
Counter22_COUT Counter22_COUT_inst0(.CLK(CLKIN), .COUT(Counter22_COUT_inst0_COUT), .O(Counter22_COUT_inst0_O));
assign D5 = Counter22_COUT_inst0_O[21];
endmodule



In [7]:

    
%%bash
cd build
yosys -q -p 'synth_ice40 -top main -blif blink_coreir.blif' blink_coreir.v
arachne-pnr -q -d 1k -o blink_coreir.txt -p blink_coreir.pcf blink_coreir.blif 
icepack blink_coreir.txt blink_coreir.bin
#iceprog blink_coreir.bin









    



/Users/hanrahan/git/magmathon/notebooks/advanced/build



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