$\Sigma-\Delta$-modulator phase noise in fractional-N PLL's

Library imports

Introduction

The first time that I needed to design a fractional-N PLL if took me quite some time to gain confidence over the model I was using to calculate the phase noise produced by the $\Sigma\Delta$-modulators(SDM). The reason for that is that there are a couple of mathematical pitfalls that are difficult to avoid at first. Many times I tough that a reference code would have made my life much simpler. This is one of those topics where a notebook including both theory and code seems particular appealing.

This entry expose first the SDM theory in the first section, the second section shows how a mash SDM works and explain the model in Python and the last section show the results and the comparison with the theoretical model. The SDM model is part of a more general package to design PLL's that is available in github.

Linear phase noise analysis for the excess of phase noise at the output of a fractional divider using a $\Sigma-\Delta$ modulator

The circuit in figure 1 implements the fractional division of input $f_{in}$ by the fractional period defined by $N+f(z)$ using a SDM. As it is difficult to design a reliable circuit that divides a input frequency by a fractional number a integer divider with a division factor that is in average the desired value is used. This operation introduces unwanted phase changes in the output signal and we are interested the power spectral density of these disturbances.

Figure 1. Topology of a fractional divider made with a SDM

The instantaneous frequency division of the divider in the figure is given by:

$$\begin{equation} N_{div}(z) = N+f(z)+H_{s}(z) \Delta_{q}(z), \end{equation}$$

Where $N$ is that integer part of the division ratio, $f(z)$ is the fractional part, and $H_s(z) \Delta_{q}(z)$ is the instantaneous error made by a SDM of order m. The instantaneous noise of the SDM has two components $\Delta_{q}(z)$ is the quantization noise and $H_s(z)$ is the noise shaping transfer function of the SD modulator.

The output frequency of the SD modulator is given by:

$$\begin{equation} f_{div}(z) = \frac{f_{in}}{N+f(z)+H_s(z) \Delta_{q}(z)}, \end{equation}$$

that can be simplified, using the approximation $\frac{1}{1+x} \approx 1-x \: \text{for } x << 1$, as:

$$\begin{equation} f_{div}(z) = \frac{f_{in}}{N+f(z)}\left(1 - \frac{H_s(z) \Delta_{q}(z)}{N+f(z)}\right), \end{equation}$$

As $\frac{f_{in}}{N+f(z)}$ equals the target frequency, which in a PLL is the reference frequency $f_{ref}$, the frequency error as a function of the target frequency equals:

$$\begin{equation} \Delta_{f_{div}}(z) = - f_{ref} \frac{ H_s(z) \Delta_{q}(z)}{N+f(z)}. \end{equation}$$

The power spectral density of the quantization noise can be approximated using a similar assumption than the one used to calculate the spectrum of the quantization noise of a ADC. With a minimun steps size $\delta$ equals two one the power of the errro can be approximated by:

$$\begin{equation} \Delta_{q}^2 = \frac{1}{12} (step^2), \end{equation}$$

this noise is uniformly distributed over the Nyquist bandwidth of the sampler, than in the case of a PLL is $f_{ref}/2$, and it has a power spectral density given by:

$$\begin{equation} \Delta_{q}^2 = \frac{1}{6 f_{ref}} (step^2/Hz). \end{equation}$$

The other aspect that needs to be accounted for, in order to find a close expression for the phase noise, is the shaping of the SDM, for Mash-1-1-1 SDM this is given by[1]:

$$\begin{equation} H_s(z)= (1-z^{-1})^m, \end{equation}$$

where m is the SDM order.

With this elements in place it is possible to have a better expression for the error made approximating the frequency, thus:

$$\begin{equation} \Delta_{f_{div}}(z)^2 = \left|f_{ref} \frac{ (1-z^{-1})^m}{N+f(z)}\right|^2 \frac{1}{6 f_{ref}}. \end{equation}$$

As it happens we are interesting in the phase, and this is calculated by integrating the last expression in the z-domain. Then we have:

$$\begin{equation} \Phi_{div}(z) = \frac{2 \pi T_{ref} \Delta_{f_{div}}(z)}{1-z^{-1}}, \end{equation}$$

that putting everything together ends being:

$$\begin{equation} \Phi_{div}(z)^2 = \frac{(2 \pi)^2}{6 f_{ref}} \frac{|1-z^{-1}|^{2(m-1)}}{(N+f(z))^2}(Rad^2/Hz) \end{equation}$$

by definition $\mathcal{L}(z)= \Phi_{div}(z)^2/2$, then:

$$\begin{equation} \mathcal{L}(z) = \frac{(2 \pi)^2}{12 f_{ref}} \frac{|1-z^{-1}|^{2(m-1)}}{(N+f(z))^2}(Rad^2/Hz), \end{equation}$$

that can be replaced by a more useful expression where $z$ is replaced by $e^{sT_{ref}}$. Calling the frequency offset $f_m$, to emphasis that this is the frequency offset due to modulation, the result is:

$$\begin{equation} \mathcal{L}(f_m) = \frac{(2 \pi)^2}{12 f_{ref}} \frac{[2 sin(\pi f_m/ f_{ref})]^{2(m-1)}}{(N+f(z))^2}. \end{equation}$$

As presented here this is the noise at the output of the divider, normally in previous references, [1] and [2], the noise is calculated at the input of the divider, but I consider this clearer. If the equivalent noise at the input of the divider needs to be calculated that can be done by simply multipling the last equation by $(N+f(z))^2$.

Using the pnoise module and the sdmod to simulate a SDM

Within the plldesigner project two modules implement a class for adding pnoise frequency domain signals and creating SDM sequences.

The sigma delta modulator is implemented by an algorithm that uses a counter that add every time the input word K and overflows when the value reaches MAX. MAX is the maximum value of the SDM register, that is: $2^N-1$, for a register of N bits. The next code shows how a first order modulator is implemented:

The implementation of first, second and third order Sigma-delta modulators can be found in: plldesigner

Creating a SDM sequence with the sdmod module

In order to create a 1-1-1 Mash sequence the gen_mash function was created in the sdmod module. The function has as inputs, the order of the modulator m, number of bits of the accumulator and the input vector $k[n]$. The following code shows the sequence created by a SDM of third order.

The phase error $\phi_{out}[n]$ can be calculated integrating the error in the frequency. Then the power spectrum density is estimated with the welch periodogram.

Non-linear behavior of the $\Sigma-\Delta$ modulator

The previous theory fails to predict spurs that can occur when the input is a rational number. This is demonstrated using the same SDM but with a input equivalent to 1/8. It is important to understand these spurs as they can fall in band after they are folded back by the non-linearity of the CP and the PFD.

The spurs appearance and amplitude depend both of the input word and the initial state of the registers of the modulator [3]. It can be that initializing the first register of the first register of the SDM creates enough dithering to reduce the spurs The gen_mash accepts a fourth argument to initialize the mash registers. This argument is a tuple with a number of elements that equals the order of the SDM.

Conclution

With this entry I revisited the theory of SD modulators using a module written in Python. The fundamental aspects of Mash SDM modulators are explained and documented. To analyse the output I used the nice Scipy library. In this way, and with the help of the Ipython notebook, the linear theory of mash SDM and its limitations are well documented and results are easily replicated.

This shows what would be the intention with the plldesigner toolkit. This a project that I have been developing and aims to add specific functionality to the numpy+scipy+ipython ecosystem to simulate and model PLL's.

References

1. B. Miller and R. J. Conley, “A multiple modulator fractional divider,” IEEE Transactions on Instrumentation and Measurement, vol. 40, no. 3, pp. 578–583, 1991.

2. T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553–559, May 1993.

3. Kozak, M., Kale, I., "Rigorous analysis of delta-sigma modulators for fractional-N PLL frequency synthesis," IEEE Transactions on Circuits and Systems I: Regular Papers 51, 1148–1162, 2004. (doi:10.1109/TCSI.2004.829308)

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