In [1]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/fig-20-15.png'))
Caracteristicas usadas en las simulaciones:
In [2]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/long-channel-mosfet.png'))
In [3]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/table-9-1.png'))
Archivo: Fig-20-15-LEVEL-3.cir
Fig-20-15-LEVEL-3.cir Barrido de VDD de 0 a 10 V
In [4]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_ngspice_Level_3.png'))
Fig-20-15-LEVEL-3.cir Transitorio de 0 a 1n Segundo, condicines iniciales v(gateM1)=0 v(drainM2)=0
In [6]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_ngspice_Level_3_transitory.png'))
Fig-20-15-LEVEL-3.cir Transitorio de 0 a 1n Segundo, condicines iniciales v(gateM1)=5 v(drainM2)=0
In [7]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_ngspice_Level_3_transitory_2.png'))
Circuito en esquematico:
In [8]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_electric_sch.png'))
Circuito en esquematico para exportar a Spice:
In [13]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_electric_sch_2.png'))
Edicion de las preferencias para seleccionar nivel 3
In [14]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_electric_preferences.png'))
Simulacion en LTSpice, Archivo: Current_mirror_bias_SIM_long_channel.spi , Barrido de VDD de 0 a 6 V
In [15]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_ltspice_sch.png'))
Circuito en LayOut:
In [16]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_electric_layout.png'))
Circuito en LayOut para exportar a Spice:
In [17]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_electric_layout_sim.png'))
In [19]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_electric_layout_2.png'))
Simulacion en LTSpice, Archivo: Current_mirror_bias_layout_SIM.spi , Barrido de VDD de 0 a 6 V
In [20]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_ltspice_layout.png'))
Libreria final, archivo: Fig-20-15-Sim.jelib
In [1]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_15_jelib.png'))
In [2]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Fig_20_22.png'))
Caracteristicas usadas en las simulaciones:
In [3]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/short_channel_model.png'))
In [4]:
from IPython.core.display import Image, display
display(Image(url='images/taller-oct-6/Table_9_2.png'))
In [ ]: